naps.cores.peripherals package¶
Submodules¶
naps.cores.peripherals.bitbang_i2c module¶
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class
naps.cores.peripherals.bitbang_i2c.
BitbangI2c
(*args, src_loc_at=0, **kwargs)¶ Bases:
nmigen.hdl.ir.Elaboratable
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elaborate
(platform: naps.soc.soc_platform.SocPlatform)¶
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naps.cores.peripherals.bitbang_spi module¶
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class
naps.cores.peripherals.bitbang_spi.
BitbangSPI
(*args, src_loc_at=0, **kwargs)¶ Bases:
nmigen.hdl.ir.Elaboratable
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elaborate
(platform: naps.soc.soc_platform.SocPlatform)¶
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naps.cores.peripherals.csr_bank module¶
naps.cores.peripherals.csr_bank_zynq_test module¶
naps.cores.peripherals.drp_bridge module¶
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class
naps.cores.peripherals.drp_bridge.
DrpBridge
(*args, src_loc_at=0, **kwargs)¶ Bases:
nmigen.hdl.ir.Elaboratable
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elaborate
(platform: naps.soc.soc_platform.SocPlatform)¶
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class
naps.cores.peripherals.drp_bridge.
DrpInterface
(DWE, DEN, DADDR, DI, DO, DRDY, DCLK)¶ Bases:
object
naps.cores.peripherals.mmio_gpio module¶
naps.cores.peripherals.soc_memory module¶
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class
naps.cores.peripherals.soc_memory.
SocMemory
(*args, src_loc_at=0, **kwargs)¶ Bases:
nmigen.hdl.ir.Elaboratable
A memory that can be read / written to by the soc
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elaborate
(platform)¶
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handle_read
(m, addr, data, read_done)¶
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handle_write
(m, addr, data, write_done)¶
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read_port
(domain='sync', **kwargs)¶
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write_port
(domain='sync', **kwargs)¶
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