naps.platform package

Subpackages

• naps.platform.plugins package
  • Submodules
  • naps.platform.plugins.hdmi_plugin_resource module
  • naps.platform.plugins.plugin_connector module
  • naps.platform.plugins.usb3_plugin_resource module
  • Module contents

Submodules

naps.platform.beta_platform module

class naps.platform.beta_platform.BetaPlatform

Bases: nmigen_boards.microzed_z020.MicroZedZ020Platform

connect_mainboard()

class naps.platform.beta_platform.BetaRFWPlatform

Bases: nmigen.vendor.lattice_machxo_2_3l.LatticeMachXO2Or3LPlatform

connectors = []

device = 'LCMXO2-2000HC'

package = 'TG100'

resources = [(resource pic_io 0 (subsignal ss (pins io 27) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal sck (pins io 31) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal sdo (pins io 32) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal pb22b (pins io 47) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal sn (pins io 48) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal sdi (pins io 49) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal done (pins io 76) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')) (subsignal initn (pins io 77) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP' DRIVE='4')))]

speed = '6'

naps.platform.colorlight_5a_75b_7_0 module

class naps.platform.colorlight_5a_75b_7_0.Colorlight5a75b70Platform(*, toolchain='Trellis')

Bases: nmigen.vendor.lattice_ecp5.LatticeECP5Platform, abc.ABC

connectors = [(connector j 1 1=>F3 2=>F1 3=>G3 5=>G2 6=>H3 7=>H5 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 2 1=>J4 2=>K3 3=>G1 5=>K4 6=>C2 7=>E3 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 3 1=>H4 2=>K5 3=>P1 5=>R1 6=>L5 7=>F2 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 4 1=>P4 2=>R2 3=>M8 5=>M9 6=>T6 7=>R6 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 5 1=>M11 2=>N11 3=>P12 5=>K15 6=>N12 7=>L16 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 6 1=>K16 2=>J15 3=>J16 5=>J12 6=>H15 7=>G16 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 7 1=>H13 2=>J13 3=>H12 5=>G14 6=>H14 7=>G15 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 8 1=>A15 2=>F16 3=>A14 5=>E13 6=>B14 7=>A13 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12)]

default_clk = 'clk25'

device = 'LFE5U-25F'

generate_openocd_conf()

package = 'BG256'

program_fatbitstream(name, **kwargs)

resources = [(resource clk25 0 (pins io P6) (clock 25000000.0) (attrs GLOBAL=True IO_TYPE='LVCMOS33')), (resource led 0 (pins o P11) (attrs IO_TYPE='LVCMOS33')), (resource user_led 0 (pins-n o P11) (attrs IO_TYPE='LVCMOS33')), (resource button 0 (pins i M13) (attrs IO_TYPE='LVCMOS33')), (resource user_btn 0 (pins-n io M13) (attrs IO_TYPE='LVCMOS33')), (resource uart 0 (subsignal rx (pins i P11)) (subsignal tx (pins o M13)) (attrs IO_TYPE='LVCMOS33')), (resource sdram_clock 0 (pins io C6) (attrs IO_TYPE='LVCMOS33')), (resource sdram 0 (subsignal a (pins io A9 E10 B12 D13 C12 D11 D10 E9 D9 B7 C8)) (subsignal dq (pins io B13 C11 C10 A11 C9 E8 B6 B9 A6 B5 A5 B4 B3 C3 A2 B2 E2 D3 A4 E4 D4 C4 E5 D5 E6 D6 D8 A8 B8 B10 B11 E11)) (subsignal we_n (pins io C7)) (subsignal ras_n (pins io D7)) (subsignal cas_n (pins io E7)) (subsignal ba (pins io A7)) (attrs IO_TYPE='LVCMOS33')), (resource eth_clocks 0 (subsignal tx (pins io M2)) (subsignal rx (pins io M1)) (attrs IO_TYPE='LVCMOS33')), (resource eth 0 (subsignal rst_n (pins io P5)) (subsignal mdio (pins io T2)) (subsignal mdc (pins io P3)) (subsignal rx_ctl (pins io N6)) (subsignal rx_data (pins io N1 M5 N5 M6)) (subsignal tx_ctl (pins io M3)) (subsignal tx_data (pins io L1 L3 P2 L4)) (attrs IO_TYPE='LVCMOS33')), (resource eth_clocks 1 (subsignal tx (pins io M12)) (subsignal rx (pins io M16)) (attrs IO_TYPE='LVCMOS33')), (resource eth 1 (subsignal rst_n (pins io P5)) (subsignal mdio (pins io T2)) (subsignal mdc (pins io P3)) (subsignal rx_ctl (pins io L15)) (subsignal rx_data (pins io P13 N13 P14 M15)) (subsignal tx_ctl (pins io R15)) (subsignal tx_data (pins io T14 R12 R13 R14)) (attrs IO_TYPE='LVCMOS33')), (resource usb 0 (subsignal d_p (pins io M8)) (subsignal d_n (pins io R2)) (subsignal pullup (pins io P4)) (attrs IO_TYPE='LVCMOS33'))]

speed = '8'

naps.platform.hdmi_digitizer_platform module

class naps.platform.hdmi_digitizer_platform.HdmiDigitizerPlatform

Bases: nmigen_boards.te0714_03_50_2I.TE0714_03_50_2IPlatform

naps.platform.micro_r2_platform module

class naps.platform.micro_r2_platform.MicroR2Platform

Bases: nmigen_boards.zturn_lite_z010.ZTurnLiteZ010Platform

naps.platform.usb3_plugin_platform module

class naps.platform.usb3_plugin_platform.Usb3PluginPlatform

Bases: nmigen.vendor.lattice_machxo_2_3l.LatticeMachXO2Or3LPlatform

connectors = []

device = 'LCMXO2-2000HC'

generate_openocd_conf()

package = 'TG100'

program_fatbitstream(name, **kwargs)

resources = [(resource ft601 0 (subsignal reset (pins-n o 4) (attrs IO_TYPE='LVCMOS33')) (subsignal data (pins o 75 74 70 69 68 67 66 65 64 61 60 59 58 57 54 53 83 84 85 86 87 88 96 97 98 99 7 8 21 24 20 25) (attrs IO_TYPE='LVCMOS33')) (subsignal be (pins o 19 18 17 16) (attrs IO_TYPE='LVCMOS33')) (subsignal oe (pins-n o 9) (attrs IO_TYPE='LVCMOS33')) (subsignal read (pins-n o 10) (attrs IO_TYPE='LVCMOS33')) (subsignal write (pins-n o 12) (attrs IO_TYPE='LVCMOS33')) (subsignal siwu (pins-n o 13) (attrs IO_TYPE='LVCMOS33')) (subsignal rxf (pins-n i 14) (attrs IO_TYPE='LVCMOS33')) (subsignal txe (pins-n i 15) (attrs IO_TYPE='LVCMOS33')) (subsignal gpio (pins io 2 1) (attrs IO_TYPE='LVCMOS33')) (subsignal wakeup (pins-n io 3) (attrs IO_TYPE='LVCMOS33')) (subsignal clk (pins i 63) (clock 100000000.0) (attrs IO_TYPE='LVCMOS33')) (subsignal clk1 (pins i 62) (clock 100000000.0) (attrs IO_TYPE='LVCMOS33'))), (resource led 0 (pins o 71) (attrs IO_TYPE='LVCMOS33')), (resource plugin_stream_input 0 (subsignal valid (diffpairs i (p 45) (n 47)) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')) (subsignal lvds0 (diffpairs i (p 42) (n 43)) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')) (subsignal lvds1 (diffpairs i (p 40) (n 41)) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')) (subsignal lvds2 (diffpairs i (p 36) (n 37)) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')) (subsignal lvds3 (diffpairs i (p 29) (n 30)) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')) (subsignal clk_word (diffpairs i (p 34) (n 35)) (clock 50000000.0) (attrs IO_TYPE='LVDS25' DIFFRESISTOR='100')))]

speed = '6'

naps.platform.zybo_platform module

class naps.platform.zybo_platform.ZyboPlatform(*, toolchain='Vivado')

Bases: nmigen.vendor.xilinx_7series.Xilinx7SeriesPlatform

connectors = []

device = 'xc7z010'

package = 'clg400'

resources = [(resource hdmi north (subsignal clock (diffpairs o (p H16) (n H17)) (attrs IOSTANDARD='TMDS_33')) (subsignal b (diffpairs o (p D19) (n D20)) (attrs IOSTANDARD='TMDS_33')) (subsignal g (diffpairs o (p C20) (n B20)) (attrs IOSTANDARD='TMDS_33')) (subsignal r (diffpairs o (p B19) (n A20)) (attrs IOSTANDARD='TMDS_33')) (subsignal out_en (pins o F17) (attrs IOSTANDARD='LVCMOS33')))]

speed = '1'

Module contents