naps.soc package

Submodules

naps.soc.cli module

naps.soc.cli.cli(top_class, runs_on, possible_socs=(None))

naps.soc.csr_types module

class naps.soc.csr_types.ControlSignal(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ast.Signal, naps.soc.csr_types._Csr

Just a Signal. Indicator, that it is for controlling some parameter (i.e. can be written from the outside) Is mapped as a CSR in case the design is build with a SocPlatform.

class naps.soc.csr_types.EventReg(*args, src_loc_at=0, **kwargs)

Bases: naps.soc.csr_types._Csr

A “magic” register, that doesnt have to be backed by a real register. Useful for implementing resets, fifo interfaces, … The logic generated by the handle_read and handle_write hooks is part of the platform defined BusSlave and runs in its clockdomain.

class naps.soc.csr_types.PulseReg(*args, src_loc_at=0, **kwargs)

Bases: naps.soc.csr_types.EventReg, nmigen.hdl.ir.Elaboratable

A register that generates one cycle wide pulses when ones are written. The pulses happen in the CSR domain. Use a PulseSynchronizer to get one cycle wide pulses in another domain, so long as its clock speed is not slower than the CSR domain.

elaborate(platform)
class naps.soc.csr_types.StatusSignal(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ast.Signal, naps.soc.csr_types._Csr

Just a Signal. Indicator, that it is for communicating the state to the outside world (i.e. can be read but not written from the outside) Is mapped as a CSR in case the design is build with a SocPlatform.

naps.soc.devicetree_overlay module

naps.soc.devicetree_overlay.devicetree_overlay(platform, overlay_name, overlay_content, placeholder_substitutions_dict=None)

naps.soc.fatbitstream module

class naps.soc.fatbitstream.CommandPosition(value)

Bases: enum.Enum

An enumeration.

Back = 2
BeforeBitstream = 3
Front = 1
class naps.soc.fatbitstream.FatbitstreamContext(platform, called_by_get_classmethod=False)

Bases: object

add_cmd_unique(new_cmd: str, new_pos=<CommandPosition.Back: 2>)
add_cmds(new_cmds: Union[str, Iterable[str]], new_pos=<CommandPosition.Back: 2>)
generate_fatbitstream(file: BinaryIO, build_name: str, build_products: nmigen.build.run.BuildProducts)
classmethod get(platform)

Implements a singleton-like pattern here to have exactly one FatbitstreamContext per Platform instance :rtype: FatbitstreamContext

platform_to_context_dict = {}
class naps.soc.fatbitstream.File(name, contents)

Bases: object

naps.soc.hooks module

naps.soc.hooks.address_assignment_hook(platform, top_fragment: nmigen.hdl.ir.Fragment, sames: naps.soc.tracing_elaborate.ElaboratableSames)
naps.soc.hooks.csr_and_driver_item_hook(platform, top_fragment: nmigen.hdl.ir.Fragment, sames: naps.soc.tracing_elaborate.ElaboratableSames)
naps.soc.hooks.peripherals_collect_hook(platform, top_fragment: nmigen.hdl.ir.Fragment, sames: naps.soc.tracing_elaborate.ElaboratableSames)

naps.soc.memorymap module

class naps.soc.memorymap.Address(address, bit_offset, bit_len=None, bus_word_width=32)

Bases: object

bits_of_word(word_address: int)

If the Address is part of the addressed word it returns a tuple of the range of own addressed bits and of the bits of the word. otherwise it returns None. :param word_address: the base address of the word. this is not an Address object but rather an int because we need only the base address. :return a tuple of (word_range, signal_range)

collides(other_address)
static parse(obj, bus_word_width=32)

Parse an address object from either a string or pass an address object or none through. :param obj: either a string in the format 0xABCD[optional_python:slice] or an Address object or None :param bus_word_width: the native word width of the underlying bus in bits. :return: an address object or None

range()

Return a range(start_byte, end_byte)

translate(other)

Translate an other address by the current address :param other: the address to translate :return: the translated address

class naps.soc.memorymap.MemoryMap(*args, src_loc_at=0, **kwargs)

Bases: nmigen._unused.MustUse

property absolute_range_of_direct_children
add_alias(name, obj)

Adds an alias to a resource somewhere else in the hierarchy. :param name: the name of the resource :param obj: the object with which one can find the other resource

add_driver_item(name, driver_item)
allocate(name, writable, bits=None, address=None, obj=None)

Allocate / add a resource to the memorymap. :param name: the name of the resource :param writable: a boolean indicating if the resource is writable :param bits: the width of the peripheral :param address: the address to place the resource to (optional) :param obj: an object to attach to that memory location. In the case of hierarchical memorymaps, this is the sub memorymap :return: the address of the resource

allocate_subrange(subrange, name=None, place_at=None)

Add a sub-memorymap to the Memorymap. :type subrange: MemoryMap :param name: the name of the subrange. If None the subrange be inlined into this memorymap and no hierarchy will be created. :param subrange: The subrange to add :param place_at: The desired location of the memorymap fragment. Overrides the subranges preference. :return: The address where the subrange is placed

property bus_word_width_bytes
property byte_len

Calculate the size (based on the resource with the highest address part) of the memorymap :return: the size of the memorymap in bytes (aligned to the bus word width)

property direct_children
property direct_children_byte_len

Calculate the size (based on the _normal_ resource with the highest address part) of the memorymap :return: the size of the memorymap in bytes (aligned to the bus word width)

find_recursive(obj, go_up=False)

Searches recursively for the given object and returns the associated address. If the object is not found, None is returned :param go_up: Determine if we should search upwards in the hierarchy if we are not the top memorymap :rtype: Address :param obj: the object to look for

property flattened
property is_empty
is_free(check_address)

Check if the provided address is free. :param check_address: the address to check. :return: A boolean indicating if the address is free

property own_offset
property path
property subranges
property top_memorymap
property was_inlined

naps.soc.peripheral module

class naps.soc.peripheral.Peripheral(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
range()
class naps.soc.peripheral.Response(value)

Bases: enum.Enum

An enumeration.

ERR = 1
OK = 0

naps.soc.peripherals_aggregator module

class naps.soc.peripherals_aggregator.PeripheralsAggregator

Bases: object

add_peripheral(peripheral)
handle_read(m, addr, data, read_done_callback)
handle_write(m, addr, data, write_done_callback)
range()

naps.soc.program_fatbitstream_local module

naps.soc.program_fatbitstream_local.program_fatbitstream_local(fatbitstream, run=False)

naps.soc.program_fatbitstream_ssh module

naps.soc.program_fatbitstream_ssh.program_fatbitstream_ssh(fatbitstream_file: pathlib.Path, *, run=False, dir='fatbitstreams', **kwargs)

naps.soc.smoke_test module

class naps.soc.smoke_test.SocSmokeTest(methodName='runTest')

Bases: unittest.case.TestCase

test_hdmi_registers(testdata=1)

naps.soc.soc_platform module

class naps.soc.soc_platform.SocPlatform(platform, *args, **kwargs)

Bases: abc.ABC

base_address = None
prepare_soc(elaboratable)
naps.soc.soc_platform.soc_platform_name(obj)

naps.soc.soc_platform_test module

class naps.soc.soc_platform_test.ConcreteSocPlatform(platform, *args, **kwargs)

Bases: naps.soc.soc_platform.SocPlatform

class naps.soc.soc_platform_test.TestSocPlatform(methodName='runTest')

Bases: unittest.case.TestCase

test_is_instance()

naps.soc.tracing_elaborate module

class naps.soc.tracing_elaborate.ElaboratableSames

Bases: object

get_by_filter(something, item_filter)
get_elaboratable(something)
get_module(something)
get_row(something)
insert(a, b)
naps.soc.tracing_elaborate.fragment_get_with_elaboratable_trace(elaboratable, platform, sames=None)
naps.soc.tracing_elaborate.inject_elaborate_wrapper(obj, sames)

Module contents