naps.cores.mipi.dsi_tx package

Submodules

naps.cores.mipi.dsi_tx.d_phy_lane module

class naps.cores.mipi.dsi_tx.d_phy_lane.DPhyClockLane(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
class naps.cores.mipi.dsi_tx.d_phy_lane.DPhyDataLane(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ir.Elaboratable

A mipi D-Phy Data lane that can handle bidirectional lp data transfer and unidirectional hs transfer.

The sync domain of this module should run at 2x the LP Hold period. Eg if the hold period is 66ns, the sync domain should run at 30 Mhz (these are reasonable values btw). This is needed to be able to sample the incoming data during bus turnaround since there is no fixed phase relation (nyquist).

elaborate(platform)

naps.cores.mipi.dsi_tx.d_phy_lane_test module

class naps.cores.mipi.dsi_tx.d_phy_lane_test.DPhyDataLaneTest(methodName='runTest')

Bases: unittest.case.TestCase

naps.cores.mipi.dsi_tx.dsi_phy module

class naps.cores.mipi.dsi_tx.dsi_phy.DsiPhy(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform: nmigen.build.plat.Platform)

naps.cores.mipi.dsi_tx.py_dsi_generator module

naps.cores.mipi.dsi_tx.py_dsi_generator.assemble(generator)
naps.cores.mipi.dsi_tx.py_dsi_generator.long_packet(data_type)
naps.cores.mipi.dsi_tx.py_dsi_generator.packet_header(data_type, payload=(const 16'd0))
naps.cores.mipi.dsi_tx.py_dsi_generator.short_packet(data_type, payload=(const 16'd0))

naps.cores.mipi.dsi_tx.types module

class naps.cores.mipi.dsi_tx.types.DsiErrorResponse(*args, **kwargs)

Bases: naps.data_structure.packed_struct.PackedStructBaseClass

CHECKSUM_ERROR: unsigned(1)
CONTENTION_DETECTED: unsigned(1)
DSI_DATA_TYPE_NOT_RECOGNIZED: unsigned(1)
DSI_PROTOCOL_VIOLATION: unsigned(1)
DSI_VC_ID_INVALID: unsigned(1)
ECC_ERROR_MULTI_BIT_NOT_CORRECTED: unsigned(1)
ECC_ERROR_SINGLE_BIT_CORRECTED: unsigned(1)
EOT_SYNC_ERROR: unsigned(1)
ESCAPE_MODE_ENTRY_COMMAND_ERROR: unsigned(1)
FALSE_CONTROL_ERROR: unsigned(1)
INVALID_TRANSMISSION_LENGTH: unsigned(1)
LOW_POWER_TRANSMIT_SYNC_ERROR: unsigned(1)
PERIPHERAL_TIMEOUT_ERROR: unsigned(1)
RESERVED: unsigned(1)
SOT_ERROR: unsigned(1)
SOT_SYNC_ERROR: unsigned(1)
class naps.cores.mipi.dsi_tx.types.DsiLongPacketDataType(value)

Bases: enum.IntEnum

An enumeration.

BLANKING_PACKET_NO_DATA = 25
DCS_LONG_WRITE = 57
GENERIC_LONG_WRITE = 41
LOOSELY_PACKET_PIXEL_STREAM_18_BIT_RGB_6_6_6 = 46
LOOSELY_PACKET_PIXEL_STREAM_20_BIT_YCBCR_4_2_2 = 12
NULL_PACKET_NO_DATA = 9
PACKED_PIXEL_STREAM_12_BIT_YCBCR_4_2_0 = 61
PACKED_PIXEL_STREAM_16_BIT_RGB_5_6_5 = 14
PACKED_PIXEL_STREAM_16_BIT_YCBCR_4_2_2 = 44
PACKED_PIXEL_STREAM_18_BIT_RGB_6_6_6 = 30
PACKED_PIXEL_STREAM_24_BIT_RGB_8_8_8 = 62
PACKED_PIXEL_STREAM_24_BIT_YCBCR_4_2_2 = 28
PACKED_PIXEL_STREAM_30_BIT_RGB_10_10_10 = 13
PACKED_PIXEL_STREAM_36_BIT_RGB_12_12_12 = 29
class naps.cores.mipi.dsi_tx.types.DsiShortPacketDataType(value)

Bases: enum.IntEnum

An enumeration.

COLOR_MODE_OFF = 2
COLOR_MODE_ON = 18
DCS_READ_0_PARAMETER = 6
DCS_SHORT_WRITE_0_PARAMETER = 5
DCS_SHORT_WRITE_1_PARAMETER = 21
END_OF_TRANSMISSION_PACKET = 8
GENERIC_READ_0_PARAMETER = 4
GENERIC_READ_1_PARAMETER = 20
GENERIC_READ_2_PARAMETER = 36
GENERIC_SHORT_WRITE_0_PARAMETER = 3
GENERIC_SHORT_WRITE_1_PARAMETER = 19
GENERIC_SHORT_WRITE_2_PARAMETER = 35
H_SYNC_END = 49
H_SYNC_START = 33
SET_MAXIMUM_RETURN_PACKET_SIZE = 55
SHUT_DOWN_PERIPHERAL = 34
TURN_ON_PERIPHERAL = 50
V_SYNC_END = 17
V_SYNC_START = 1

naps.cores.mipi.dsi_tx.video2dsi module

class naps.cores.mipi.dsi_tx.video2dsi.ImageStream2Dsi(*args, src_loc_at=0, **kwargs)

Bases: nmigen.hdl.ir.Elaboratable

Converts an ImageStream to a Packetized stream that can be fed into a DSI phy. Uses Non Burst Mode with Sync Events.

elaborate(platform)

naps.cores.mipi.dsi_tx.video2dsi_test module

class naps.cores.mipi.dsi_tx.video2dsi_test.TestDsiProtocol(methodName='runTest')

Bases: unittest.case.TestCase

test_2_lane()
test_full_stack()

Module contents